In any communication application, there may be a need for a clock signal. Such a signal may be generated from a reference frequency using a phase-locked loop (PLL). The relationship between the frequency of the incoming reference clock and that of the output of the PLL may be determined by the division ratio of a divider in the feedback path of the PLL. In an integer-N PLL, the output frequency is an integer multiple of the reference frequency. In such a PLL, the resolution of the output frequency may be limited to N times the reference frequency resolution. In some applications it may be desirable to achieve a finer resolution. One solution is to employ fractional-N PLLs, in which the output frequency may be a non-integer multiple of the reference frequency. Such a PLL may employ dual-mode dividers in the feedback path and may require a sigma-delta modulator to improve jitter degradation due to modulation of the division ratio. The complexity of the divider, its power overhead and the necessity of a sigma-delta modulator may be drawbacks of this method.
Thus, there is a need for a fractional-N PLL of low complexity that does not employ a sigma-delta modulator.